For FPGA technology development, the acquisition of Xilinx and Altera by AMD and Intel, respectively, is obviously an important turning point in this history. As FPGA companies change from independent companies to a sub-division of chip giants, their technology development strategies will also change greatly, and this article will make a prospect for such strategic development.

FPGA enables new categories of chips

First of all, with the integration with chip giants, FPGAs will be further integrated with traditional chips, giving full play to their programmability advantages, to empower new capabilities of traditional chips, and even realize new chip categories.

For Intel, such a new category of chips is an IPU (infrastructure processing unit, data center processor). With the widespread use of data centers, some important tasks in data centers including network control, storage management and network security and other processing power requirements are also increasing, as major chip companies launch their own solutions, Intel also introduced IPUs for this market. Last month, Intel just released its future roadmap for IPUs, in which we see that IPUs in the future through 2026 will include two versions, one based on ASIC high-performance and the other with FPGA-based programmable versions (including Oak Springs Canyon in 2022, Hot Springs Canyon in 2023/2024, and versions in planning in 2025/2026). Among them, the FPGA-based version of the IPU is actually an acceleration card that integrates the Intel FPGA chip and the Intel Xeon CPU, which can handle a variety of different network, storage and security protocols in a flexible way, thereby ensuring optimal programmability without worrying about compatibility issues.

In fact, FPGA solutions such as data center storage and networking have been engaged in related projects by startups in the past few years, but with the entry of giant Intel, we believe that such FPGA + CPU solutions will truly become one of the mainstream solutions. Startups engaged in related projects and obtaining financing show that the technology direction is feasible, and Intel's entry into this market brings ecological resources that startups do not have, and we believe that in the next few years, FPGAs and CPUs will be integrated in a tighter way (such as Chiplet), so as to truly make flexible programmable IPUs into a new chip category enabled by FPGAs.

Coincidentally, AMD is also actively planning to integrate Xilinx FPGAs and AMD's CPUs - at the AMD earnings conference in May, CEO Lisa Su announced that it will release CPUs integrated with Xilinx AI Engine in 2023, that is, CPUs with powerful AI computing capabilities. Until now, AI-related computing has been performed in GPUs or other specialized acceleration hardware, and Intel's efforts to optimize running AI on CPUs have not been recognized on a large scale by the market, as long as the CPU has a limited number of computing units. However, since the overall AI task is not only a neural network, but also other parts of the program execution run on the CPU, if the CPU and the AI acceleration unit can be closely coupled, the overall performance of the task will be improved, which is also estimated to be the original intention of AMD to propose a CPU that integrates FPGA AI engine, and this is also an example of FPGA enabling a new chip category.

To sum up, with the further popularization of tasks such as data centers and artificial intelligence, giants such as Intel and AMD will consider how to make full use of the flexibility of FPGAs to deal with these markets, and in the current situation, just launching FPGA products is not the best solution, but using the FPGA and other chips to integrate to launch a new chip category, which will be an important market direction for FPGAs in the future. Next, we will also predict where the most critical breakthrough point of FPGA in the future will be from the direction of technology.

Stronger integration and connectivity

As mentioned earlier, as FPGAs need to play a key role in enabling new SoCs, we believe that integration and interconnection have become an important technical key point. The integration and interconnection here include two levels: first, at the FPGA level, we believe that the FPGA chip itself will integrate more and more related IP, so that the FPGA chip itself is more functional and efficient; Another level is the integration of FPGAs and other chips in the system, and we believe that advanced packaging technologies such as chiplets and related interconnection technologies will be the core.

First of all, at the FPGA chip level, FPGAs provide flexibility, but for general-purpose modules (such as processors, etc.) are less efficient, so integrating hard IP on FPGA chips to meet the needs of efficiency and flexibility will continue to be the mainstream idea, and the number of integrated IPs will increase in the future. On the same chip, the FPGA is used as the core module, and other hard IP modules (such as CPU, Ethernet, video codec and memory control) are carried at the same time, and the FPGA and other IP are connected using on-chip interconnection solutions such as NOC. AMD/Xilinx is a pioneer in this regard, and its Versal product line roadmap can see that more and more hard IP will be integrated on the chip, and Intel's FPGAs will have similar designs in this regard. By integrating these hard IPs, FPGAs will be able to provide enhanced functionality. For Xilinx, its most critical IP is AI-related DSP, and we have also seen some new IP, such as Direct RF, which can directly support RF applications through ultra-high rate digital-to-analog conversion, and is expected to be combined with FPGA to meet the needs of various wireless communications, so that a true software radio can be realized, thus opening up new application scenarios for FPGAs. Therefore, by integrating more and more hard IP on FPGA chips, it will become an important technical path to further enhance FPGA functions and enter new application scenarios.

The second level is the integration and interconnection of FPGA and other chips at the system level, we believe that such integration will be the key to FPGA enabling new chip systems and categories, and combined with more hard IP integration on FPGA chips mentioned earlier, we believe that eventually more and more powerful FPGAs can empower more and more new chip categories and open up the market. At this level, we believe that the most critical technology path is to enable flexible and customizable heterogeneous integration in the form of advanced packaging, complemented by innovative interconnect technologies. In this regard, Intel has earlier announced the use of Advanced Packaging Technology (EMIB) to integrate FPGAs and high-speed transceivers (for data center scalability interconnects) and DRAM in a single package. At the HOTCHIPS conference later this year, Intel also had a presentation on the use of heterogeneous integration to enable innovative RF applications. The main advantage of using heterogeneous integration is its flexibility, such as the ability to integrate with different types and specifications of chip chips according to the user's needs, to achieve a compromise between maximizing performance, cost and customizability.

Similarly, AMD's plan to integrate Xilinx FGPA and CPU, although no clear technical specifications have been released, but based on AMD's previous investment in chiplets and AMD's previous related patents, we believe that chiplet technology is also likely to be used.

As the scale of such integration increases, so does the need for interconnects, which can become bottlenecks in multi-chip systems. Interconnects need to provide not only high bandwidth, but also support for important system-level functions such as caching and memory coherency. Currently, both Intel and AMD FPGAs support the related CXL protocol, and we believe that with the larger integration between FPGAs and processors and other chip dies, increasingly complex and high-speed chip interconnect will become a key technology.

Software will be key

In addition to hardware, how to maximize the efficiency of FPGAs in practical tasks is also an extremely critical issue. As FPGAs and other chips (such as CPUs) are tightly integrated to form a heterogeneous chip system, ensuring that software can take full advantage of FPGAs and avoid bottlenecks such as scheduling is a very complex but important issue. This is a challenging problem because the programming model of the FPGA and other parts of the system (such as the CPU) can be very different, so how to ensure that the software can correctly divide the tasks (that is, assign the tasks of the appropriate FPGA to the FPGA and the tasks suitable for other processors to the corresponding processor), handle scheduling and memory management reasonably, and use it in a more user-friendly form for software engineers. These are tasks that are quite different from traditional FPGA software, which is mainly aimed at front-end and back-end logic synthesis tasks.

In this area, both Intel and AMD are actively investing. For example, on Intel's IPU roadmap, an open and flexible software ecosystem is an important investment area for Intel, and correspondingly, Intel has just announced its acquisition of cross-platform heterogeneous chip software compiler company Codeplay, which is also considered by the industry to be an investment in next-generation FPGA software. At the same time, AMD also said at the earnings conference in May that it would invest heavily in the software field, which obviously includes FPGA-related software research and development. We believe that as FPGAs become an important part of new chip systems, the corresponding software ecosystem must also keep up, so that such a new paradigm of FPGA systems can truly enter the mainstream.